The present invention generally relates to memory devices for use with computers and other processing apparatuses. More particularly, this invention relates to solid-state mass storage drives and methods suitable for writing data to a volatile memory on a solid-state drive with non-block level I/O protocol commands, and persisting the data written to the volatile memory to a non-volatile memory on the solid-state drive using virtual or simulated block level I/O protocol commands.
Non-volatile solid-state memory technologies used with computers and other processing apparatuses (host computer systems) are currently largely focused on NAND flash memory technologies, with other emerging non-volatile solid-state memory technologies including phase change memory (PCM), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, and nanotechnology based storage media such as carbon nanofiber/nanotube-based substrates. These and other non-volatile solid-state memory technologies will be collectively referred to herein as solid-state mass storage media. Mainly for cost reasons, at present the most common solid-state memory technology used in solid-state drives (SSDs) are NAND flash memory components, commonly referred to as flash-based memory devices, flash-based storage devices, flash-based media, or raw flash.
Briefly, flash memory components store information in an array of floating-gate transistors, referred to as cells. The cell of a NAND flash memory component has a top gate (TG) and a floating gate (FG), the latter being sandwiched between the top gate and the channel of the cell. The floating gate is separated from the channel by a layer of tunnel oxide. Data are stored in (written to) a NAND flash cell in the form of a charge on the floating gate which, in turn, defines the channel properties of the NAND flash cell by either augmenting or opposing a charge on the top gate. This charge on the floating gate is achieved by applying a programming voltage to the top gate. Data are erased from a NAND flash cell by applying an erase voltage to the device substrate, which then pulls electrons from the floating gate. The charging (programming) of the floating gate is unidirectional, that is, programming can only inject electrons into the floating gate, but not release them.
NAND flash cells are organized in what are commonly referred to as pages, which in turn are organized in what are referred to as memory blocks (or sectors). Each block is a predetermined section of the NAND flash memory component. A NAND flash memory component allows data to be stored and retrieved on a page-by-page basis and erased on a block-by-block basis. For example, erasing cells is described above as involving the application of a positive voltage to the device substrate, which does not allow isolation of individual cells or even pages, but must be done on a per block basis. As a result, the minimum erasable size is an entire block, and erasing must be done every time a cell is being re-written.
In order to map a storage space of an SSD from a block level protocol viewpoint onto a physical flash storage array, the SSD presents a number of storage sectors, each sector contains typically 512 Bytes or 4096 Bytes, that may be accessed by a host computer system via an address called the Logical Block Address (LBA). A write or read command received from the host in the block level protocol identifies a start sector LBA and a number of sectors to transfer. Although a page of data is the smallest amount of data that can be written to the flash device, a page can only be written after a complete block (referred to herein as an erase block) containing that page of data has been erased. Unlike many other types of storage media, the flash storage array has a limited lifetime for each erase block, both in terms of a number of times it may be erased and re-written, that is, programmed, giving rise to a measure of Program/Erase (P/E) cycles, as well as in terms of a period of time the erase block will retain the data, that is, the retention period, where over time the programmed electrical charge will leak so that data may be lost.
To solve these issues and ensure that many writes to the same LBA by the host (for example, due to many modifications by the host to the same file on the SSD) do not prematurely wear out a single erase block, a Flash Translation Layer (FTL) function is used by the flash controller. This virtualizes the flash storage elements where the LBA used by the host is mapped to a physical address on the flash devices, but where this mapping can change each time the LBA is written to by the host. This mapping means that any sector of host data can in principle be mapped to any flash storage element. In addition, by using dynamic mapping from host LBAs to physical addresses, it can be ensured that each flash storage element is programmed at a similar rate, a function known as wear-leveling. As the drive is progressively used, some host LBAs are over-written or become unused (when a host filesystem deletes a file it generally marks the LBA as unused, to be re-used later), which means that some of the data in the flash storage array is no longer required—whereby a flash block may contain a mixture of valid and invalid data in its pages.
To enable the re-use of pages with invalid data, the FTL runs software called garbage collection which copies the valid data pages from blocks containing invalid data pages to fresh, erased blocks, thereby invalidating all the data pages in the original blocks and allowing them to be erased. This de-fragments the valid data pages, bringing them together in blocks containing only valid data pages and as a by-product creating additional erased blocks from the original fragmented blocks with valid and invalid pages that can be used to store new host write data. The FTL uses complex algorithms to decide which blocks should be candidates for the next garbage collection, based on the amount of valid data in a block, the number of times a block has been programmed, etc. As can be seen, the FTL has to perform many complex functions to store the host data efficiently.
While an SSD using flash memory offers many advantages over other mass storage media like hard disk drives, such as increased speed of read and write access, it is still much slower in operation than dynamic RAM (DRAM) technology used as main system memory in computer systems. Applications such as In-Memory Databases (IMDBs), make extensive use of the host computer DRAM to achieve the required high speed data throughputs, to the extent that the complete database is held in fast DRAM (hence their name) in order to provide the fastest possible database processing throughputs. A database may easily extend to several gigabytes in size and while the cost of DRAM has reduced in recent times, the provision of DRAM storage in Gigabyte quantities is still much more expensive when compared to NAND flash based SSD storage.
The amount of DRAM available to an IMDB is therefore constrained largely by cost, and once the DRAM capacity is reached, or if the data is required for later reference or further processing while still continuing to process new data in the meantime, the DRAM contents may be required to be ‘paged out’ to mass storage such as an SSD or HDD. DRAM is also volatile, meaning it may be required to be kept powered up by backup power supplies lest it be lost in the event of a power failure, whereas NAND flash memory is non-volatile and therefore can retain, or persist, data that is stored even if a power failure is experienced.
In view of the above, it can be appreciated that there are certain problems, shortcomings or disadvantages associated with the prior art, and that it would be desirable if a solid-state mass storage device and method for persisting volatile data located on a solid-state mass storage device to a nonvolatile memory device also located on the solid-state mass storage device were available.